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Tech · AI

Google's AI Chips Break Into Meta's Production Data Centers

For the first time, Google’s custom silicon is running major AI workloads in Meta’s infrastructure, marking a significant shift away from Nvidia's exclusive dominance.

By Anna Nowak ·

Google’s tensor processing units (TPUs) are now officially running AI workloads in production at Meta, marking the first time these custom chips have been sold to an external customer for large-scale deployment. This milestone, announced via Google’s developer blog, signals a tangible shift in the AI hardware landscape as Meta adopts a new PyTorch-native version of the SGLang inference engine. The move allows Meta to run its models on Google silicon without the friction of rewriting code for a different framework.

The transition represents a significant departure from previous methods. Historically, using TPUs required developers to work within Google’s JAX framework. The newly released SGLang-TorchTPU and the open-sourced vLLM-TorchTPU change that dynamic by making TPUs a native option for PyTorch. Zongwei Zhou, Meta’s lead for PyTorch-TPU, confirmed that the system is live in production today. He noted that this achievement resulted from a close three-way collaboration between Meta, Google, and the SGLang team. Zhou described the outcome as a remarkably mature, PyTorch-native serving stack for Meta’s operations.

Meta has long resisted being tied to a single hardware provider. Jana van Greunen, director of PyTorch engineering at Meta, emphasized that the company cannot be constrained by one architecture. She stated that the new TorchTPU integration enables Meta to deploy its existing PyTorch workloads directly onto Google’s TPUs. Google confirmed it co-developed this specific integration with Meta’s PyTorch team to ensure a smooth workflow for their engineers.

This is not the first time Meta and Google have intersected on hardware, but this is the first production-scale commitment. In the past, Meta’s research teams used TPUs via the older PyTorch/XLA bridge between 2020 and 2023 before those contracts were canceled. Google’s current push with PyTorch on TPU was specifically aimed at Meta, which previously avoided migrating to JAX. While the exact location of these production chips is not public, reports from last year suggested negotiations included Google Cloud rentals for 2026 and potential purchases for 2027, culminating in a multi-year rental agreement.

The timing of this announcement is strategic. It landed just one day after Amazon announced it was open-sourcing TorchNeuron, a native PyTorch backend for its Trainium2 and Trainium3 chips. Both moves appear designed to loosen Nvidia’s software lock-in, giving AI developers more flexibility in where they run their models. For Pacific Northwest readers, this is particularly relevant as both Google and Amazon maintain significant data center footprints in the region.

Performance metrics suggest the new setup is competitive. Inferact, the startup behind vLLM, reported that a tuned vLLM setup serving the open-weight Kimi K3 model topped 700 tokens per second for a single user on the seventh-generation Ironwood TPU. This test utilized 16 Ironwood chips with speculative decoding, a technique that speeds up inference using a smaller draft model. In comparison, the same model on 16 Nvidia GB200s reached 452 tokens per second. Without speculative decoding, the new kernels for Kimi K3 and Qwen 3.8 27B delivered roughly 1.4 to 2 times the throughput of the GB200 baseline at small batch sizes.

The ecosystem is already expanding to include more models. SGLang-TorchTPU will begin adding support for DeepSeek V4.1 Flash and Reflection Beam soon. RadixArk, the startup founded by the SGLang creators, is working toward Day 0 TPU support for new open models, aiming to have support ready on release day by the first quarter of 2027. This rapid expansion indicates a serious commitment to making TPUs a viable alternative to Nvidia GPUs for open-source AI development.

Stakeholders plan to share more details at the SGLang Summit 2026, scheduled for November 12–13 in San Francisco. The event will likely provide deeper insights into the technical architecture and future roadmap for these integrations. As the industry moves away from a single-vendor monopoly, these partnerships between major tech firms are setting the stage for a more diversified and competitive AI hardware market.

Source: Tom's Hardware

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